EDN

Wafer Level Chip Size Package

This application note provides guidelines for the use of Wafer Level Chip Size Packages (WLCSP). The information in this application note can be used throughout the various stages of WLCSP use. This ...
EDN

Reportlinker Adds Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in Substrate

Historically, embedded IC package technology is not new at all: several players such as Freescale with its RCP, Infineon with its eWLB and Ibiden for die embedding into PCB laminated substrates have ...
Nasdaq

Akoustis Locks Process Flow for First Wafer-Level-Chip-Scale Package (WLCSP) for XBAW Filters

Charlotte, N.C., Feb. 01, 2021 (GLOBE NEWSWIRE) -- Akoustis Technologies, Inc. (NASDAQ: AKTS) (“Akoustis” or the “Company”), an integrated device manufacturer (IDM) of patented bulk acoustic wave (BAW ...
Electronic Design

Wafer-Level Chip-Scale Package Favors Small-Form-Factor ASICs

A fully qualified, high-performance, low-power and small-form-factor wafer-level chip-scale package (W-CSP) developed by Oki Semiconductor satisfies a wide range of ASIC design demands. Targeting chip ...
Semiconductor Engineering

Electroplating IC Packages

The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. Applied Materials recently rolled out an ECD system for IC ...
Electronic Design

Microchip Expands UNI/O EEPROM Line With Wafer-Level Chip-Scale And TO-92 Packages

Microchip has developed a single-I/O bus UNI/O EEPROM devices in miniature, wafer-level chip-scale and TO-92 packages, in addition to the 3-pin SOT-23 package. Measuring 0.85 mm x 1.38 mm, the ...
Nasdaq

Aehr Announces Shipment of Initial FOX-XP Wafer-Level Burn-In System for Advanced AI Processors

FREMONT, CA / ACCESS Newswire / February 28, 2025 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has completed shipment of its ...
Semiconductor Engineering

Easing The Stress For Package-Level Burn-In

Considered something of a necessary evil, burn-in of IC packages during production does a great job of weeding out latent defects so they don’t turn into failures in the field. But as AI and ...
Joplin Globe

Aehr Seeing Momentum in Package-Level Burn-In Alongside Expanding Wafer-Level Burn-in Demand

FREMONT, CA / ACCESS Newswire / November 12, 2025 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in solutions, today announced the shipment of its Dual-Echo™ ...
Houston Chronicle

(BW) Wafer-Level Packaging Requirements Boost Orders for Jordan Valley Semiconductors' Advanced X-ray Metrology Systems

Semiconductor metrology equipment manufacturer Jordan Valley Semiconductors announced that they have sold, installed and qualified multiple units of their JVX 6200 system to leading memory ...
Business Wire

Invensas to Exhibit Low Temperature Wafer Bonding and 3D Interconnect Solutions at IWLPC 2016

SAN JOSE, Calif.--(BUSINESS WIRE)--Tessera Technologies, Inc. (Nasdaq:TSRA), announced today that its wholly owned subsidiary Invensas Corporation will exhibit its low temperature wafer bonding and 3D ...
Business Wire

OmniVision’s New Medical Wafer-Level Camera Module Improves Image Quality for Single-Use Endoscopy in Smallest Parts of Anatomy

SANTA CLARA, Calif.--(BUSINESS WIRE)--OmniVision Technologies, Inc., a leading developer of advanced digital imaging solutions, today announced the OVMed® OCHTA camera module with quadruple the ...